This invention relates generally to stabilizing the operational performance of MOS circuits and specifically to minimizing limitations on cascode amplifier circuit performance and reliability caused by excessive substrate current induced by hot electrons from high drain-to-source voltages.
In MOS amplifier and current mirror circuits, transistors biased into the saturation to region can experience an undesirable substrate current arising from impact ionization (due to the so-called xe2x80x9chot electronxe2x80x9d effect). Impact ionization in the MOSFET channel is described in the literature and is generally known by circuit design practitioners.
A physical model of this effect is depicted in a single p-well n-channel transistor 300 of FIG. 3. Transistor 300 is shown biased in saturation, that is, with the inversion layer 302 under the gate oxide 304 terminating short of the edge of the actual drain diffusion 306 at a pinch-off point 308. This pinch-off point 308 occurs at a drain-to-source voltage (Vds) of Vdssat. The drain current ID increases relatively little as drain-to-source voltage Vds increases beyond Vdssat. The location of the pinch-off point 308 is shown as offset from actual edge of the diffusion 306, which is the case when Vds is greater than Vdssat.
At constant gate-to-source voltage Vgs, the pinch-off point 308 moves relatively little as Vds increases. Consequently, the drain current ID changes relatively little as well. This is shown in the V-I characteristics of FIG. 5, where the ID vs. Vds operating characteristic shows the transistor operating in one of two regions, the triode region with low drain-source impedance, and the saturation region with high drain-source impedance.
Beyond Vdssat, the transistor region between the inversion layer end 308 and the edge of the drain 306 sustains nearly all of the increased voltage potential between drain and source. At sufficiently high Vds, the electric field in the depletion region between inversion layer 302 and the edge of drain 306 can cause electrons flowing from the end of the inversion layer 308 to the drain 306 (i.e., in the depletion region) to gain additional energy. With sufficient additional energy, the free carriers in the depletion region cause impact ionization, and generate additional free carriers (electron-hole pairs 320).
These additional free carriers 320 are swept out of the depletion region by the high electric field. Some of the resulting free holes flow into the P-type substrate region as majority carriers, creating a substrate current Isub that increases with Vds, as illustrated in FIG. 4. Some of the free electrons are swept into the N-type drain region as majority carriers and add to the drain current Ids. These two charge carrier flows appear as an additional component Isub of the total current in the drain and substrate terminals.
An empirical expression for the impact ionization substrate current Isub is given by,
Isub=K1 (Vds B Vdssat)*Id*(exp [xe2x88x92[K2/(Vdsxe2x88x92Vdssat)]]),
Where K1 and K2 are process-dependent parameters and Vdssat is the value of Vds where the drain characteristics enter the saturation region. Under normal operating conditions, MOS devices have essentially zero substrate current Oust the leakage current of the reverse biased drain-to-substrate depletion region), as illustrated in FIG. 4. The effect is generally much less significant in PMOS devices because the lower mobility holes in the depletion region are less efficient in creating hole-electron pairs than are the higher mobility electrons.
Differentiating this expression with respect to drain voltage, the small signal shunt conductance (gdb) from drain to substrate is given as,
gdb=K2 [ISUB]/(Vdsxe2x88x92Vdsat){circumflex over ( )}, 2.
Substituting for ISUB with the previous expression and rearranging factors produces:
gdb=K2K1(Vdsxe2x88x92Vdssat)xe2x88x921(exp[xe2x88x92[K2/(Vdsxe2x88x92Vdssat]].
FIG. 2 illustrates a plot of gdb and its inverse, rdb, for a typical NMOS transistor. rdb is the equivalent substrate current drain-to-body output resistor that would combine in parallel with the normal transistor output resistance r0. rdb is calculated for a typical NMOS transistor with K1=5 V{circumflex over ( )}xe2x88x921 and K2=30 V and plotted vs. normalized drain-source voltage, Vdsxe2x88x92Vdssat. Also plotted is the equivalent output conductance, gdb, which is the inverse of rdb. The extreme nonlinear behavior of Isub causes the parallel combination of rdb and r0 to be essentially r0 at drain voltages around Vdssat and below, since rdb is many orders of magnitude greater than typical r0.
However, at instantaneous drain-to-source voltages not much higher than a few times Vdssat, the output impedance of the transistor can be completely dominated by rdb. This is one example of how instantaneous or cumulative changes in hot-electron induced substrate current can influence the magnitude and/or variability of device characteristics. This influence can limit and sometimes defeat the possibility of achieving or maintaining desired performance circuit functionality.
As the instantaneous drain-to-source voltage of the transistor varies during operation, the instantaneous amount of the substrate current also varies causing variation of the small signal output conductance. Depending on the operating point and the output voltage swing of the cascode circuit (between the maximum required output voltage and the minimum possible output voltage), the substrate current Isub can vary dramatically. Isub can vary from a value essentially equal to zero at low and moderate Vds to a value that represents a significant portion of the total drain current as the instantaneous Vds approaches the maximum required output voltage or exceeds a critical value. The critical value of Vds (Vds=Vcrit) for the onset of significant Isub (i.e., Vds=Vcrit) depends on the available power supply voltage, the particular circuit function and performance factor(s) at issue, the transistor technology, the transistor dimensions (primarily channel length), and the bias and signal levels. Highly nonlinear circuit behavior may occur depending on the level of the output voltage. If the substrate current magnitude or the magnitude of current variation is substantial compared to the expected drain current or normal drain current variation, it may adversely effect circuit functional performance, behavior and reliability.
This critical value Vcrit depends on the details of the transistor construction, the magnitude of the instantaneous differences between drain, gate, source and substrate voltages and the drain current. The magnitude of the substrate current is a highly nonlinear function of the voltage differences and current, and can vary by orders of magnitude over very small changes in the instantaneous terminal voltages. The substrate current is affected most by the drain-to-source voltage Vds once Vds approaches Vcrit for the particular transistor technology, geometry and circuit voltage conditions.
The performance of a circuit may be affected by this radically nonlinear Isub behavior primarily in two ways. First, radical variation of ISUB may limit one or more selected characteristics of circuit performance (bias current, switching voltage threshold, switching time delay, gain, distortion, noise, and the like). A momentary increase in ISUB at a high Vds voltage above critical value Vcrit causes an unacceptable momentary change in an electrical device parameter from its nominal design value. Second, cumulative changes or drifts in a device electrical parameter e.g., parameters such as threshold voltage, transconductance, leakage current and the like may affect circuit performance. Sufficient shifts in device parameters may cause a consequent reduction of the Mean-Time-to-Failure (MTBF) for circuits of a given type, i.e. decreased reliability.
A circuit having a device with one or more electrical parameters that change rapidly with small changes of signal voltage, or output voltage level, essentially independent of the gate-source control voltage may also exhibit unacceptable changes in circuit performance, e.g., non-linear gain, distortion, impedance mismatch, and the like.
The long-term effects of excess substrate current are exhibited by slow degradation of the device electrical parameters (Vth, Gm, sub-threshold leakage, etc.). The hot carriers that cause Isub are known to cause charge trapping in the gate oxide, which, over time, causes threshold, transconductance and sub-threshold behavior shifts. Eventually, the degradation of the device parameters due to excess substrate current will reach a level where the cascode circuit performance will no longer meet the required specification and the cascode circuit will fail.
Deterioration of transistor characteristics by substrate current is known to cause undesirable changes in performance of circuits over time. The literature describes transistor modeling and circuit simulation techniques for calculating the influence of Isub on circuit behavior. Known Isub vs. Vds models (e.g., the modified Mar""s model and Sakurai""s model described elsewhere) and simulators (the known RELY simulator described elsewhere) are combined with a segmented or iterative simulation scheme.
Referring to FIG. 1 a prior art attempt to reduce degradation of performance characteristics of a simple amplifier output circuit due to substrate current and thus to improve the circuit behavior is shown. An amplifier circuit stage consisting of a simple grounded source single transistor output stage is replaced by a circuit arrangement 100 of a two transistor series combination: transistor M6A, and M6. This series combination is generally referred to as a cascode connection with M6A being the upper cascode transistor M6a and transistor M6 being the grounded source lower transistor. Upper cascode transistor M6A is interposed between the drain of the grounded source transistor and the amplifier output with its output drain node connected to amplifier output Vout and its source node connected to the drain of the grounded source transistor M6
M6 is driven by input Vin and M6A has its gate connected to a reference voltage Vref. The arrangement of transistor M6in series between output amplifier node Vout and the M6 drain node partially ameliorates degradation of the circuit gain Gc=xcex94Vout/xcex94Vin, (a selected circuit functional characteristic} and defers catastrophic failure of this functional characteristic for this particular analog circuit under a particular voltage stress. Including the Vref biased common-gate buffering transistor M6A between the drain 102 of the grounded-source output transistor M6 and the voltage output terminal Vout converts the output stage 100 into a cascode output and reduces the maximum Vds voltage stress on transistor M6 during peak output voltage excursions.
The peak substrate current Isub1 in transistor M6 before the substitution is made is about 10 ma during the peak voltage excursion (4 volts) at the output, Vout. After the substitution of the grounded-gate cascode transistor, M6A, the gate 104 of M6A is biased by Vref, a fixed voltage reference. Vref is chosen to set the gate of M6A so that the maximum Vds across transistor M6 is limited (and thus limiting the peak Isub in transistor M6) during the peak excursion of Vout.
Transistor M6A is biased so that, as the drain-source voltage Vds for transistor M6 approaches Vref minus the threshold voltage Vt of M6A, transistor M6A begins to turn off (move from the triode region to the saturation region) and absorb additional voltage supplied by source current Ido from the power supply Vdd. Vds thus will be limited to a maximum value of about Vref minus Vt. Vref and M6A limits Vds across transistor M6 to Vdsmax such that with Vdd of 10 volts and Vout at the desired 4 volts, the peak value of transistor M6 substrate current (Isub1) is reduced to essentially zero. The cascode connection causes the 4-volt peak to be shared by transistor M6 and M6A.
With Isub1 reduced to essentially zero, the gain, Gc, of the circuit is therefore stabilized so that after 115 days of simulated operation, instead of 40% degradation, there is essentially a negligible shift in gain. This provides some reduction in performance degradation sought by the inclusion of the grounded-gate transistor M6A biased to limit the peak Vds across transistor M6.
However, the cascode transistor M6A now takes up part of the voltage stress previously fully absorbed by transistor M6. Although Isub for M6A is lower than the previous value for transistor M6 (4 ma vs. 10 ma), it is still considerable. Since the operating point of M6A is biased closer to or into the triode region for low values of Vds, its impedance is lower than transistor M6 and consequently it has much less effect on the gain of the circuit 100. However, with the still relatively high value of Isub in M6A, the prospect of a stable circuit gain over a long life is not assured.
Regulated cascode circuits described in the literature can produce even higher gain than ordinary cascode circuits. See U.S. Pat. 5,039,954 by Bult et al., and U.S. Pat. No. 5,748,040 by Leung, incorporated herein by reference. Their utilization is somewhat restricted to small voltage swings and low to moderate output voltage levels because this high gain is achieved only at low drain-to-source voltage. Because their higher gain is achieved by high output impedance they are even more susceptible to hot electron induced substrate current. At higher output voltage, i.e., high Vds, the gain is reduced to levels similar to ordinary cascode circuits.
Additionally, the local feedback used in previous regulated cascode circuits generally monitor source current to maintain circuit function. However, the excess substrate current from hot-electron effects does not flow in the source loop, so is not subject to the benefits of the regulated cascode local feedback.
These and many other examples of substrate current (hot electron effects) causing limited and/or degraded circuit performance for critical circuit functional characteristics and consequent decreased reliability are known in the integrated circuit arts. Performance and reliability limitations imposed on using known circuits to provide useful circuit functions are increasing as the trend for lower device operating voltages continues over time. The ever-increasing demand for faster circuit performance impels the continuing decrease in active electrical circuit dimensions and consequent increased sensitivity to degradation by substrate current.
There is a large and pressing need to provide improvements in circuits to obviate these limitations on circuit designers and manufacturers.
MOS Cascode amplifier circuits are subject to long-term or instantaneous changes (degradation) of performance characteristics by excess substrate currents. These currents can be generated in the grounded source transistor of the cascode connected output transistors during peak excursions of drain-source voltage across the grounded source transistor when the output voltage of the MOS Cascode amplifier circuit is at a maximum. The improved Cascode amplifier circuit arrangement of the present invention includes a voltage limiting bias circuit arrangement of additional transistors. The bias circuit arrangement acts as a series voltage-limiting device between the MOS Cascode amplifier circuit output node and the drain node of the upper-most cascode connected transistors when the MOS Cascode amplifier circuit output voltage is at its maximum value. An embodiment of the improved MOS Cascode amplifier circuit arrangement is arranged to limit the drain-source voltage excursion peak on the sensitive cascode transistor to a value below a pre-selected critical voltage, Vcrit. Vcrit is defined as the drain-source voltage value for the sensitive cascode transistor for which the instantaneous and/or cumulative substrate current caused by peak drain-source voltage excursions greater than Vcrit would instantaneously or cumulatively degrade the transistor""s sensitive electrical parameters to an extent that would degrade (an) amplifier performance characteristic(s) to an appreciable degree.
The additional transistors of one embodiment of the bias circuit arrangement are connected by internal adjacent source-drain nodes as a sequential chain with gates biased at respective fixed voltages. One external drain node of the chain connects to the output node of the MOS cascode amplifier and one external source node of the chain connects to drain of the uppermost cascode connected transistors. The number of additional transistors and the fixed bias gate voltages are selected to limit the peak drain-source voltage excursion on the sensitive transistor under selected operating conditions.
Embodiments of the voltage-limiting, substrate current minimizing, bias circuit arrangement of the present circuit invention can significantly extend circuit performance, operational lifetime or significantly reduce unwanted circuit performance limitations or decreased reliability resulting from momentary or cumulative electrical parameter variation effects caused by excessive substrate current in individual transistors of over stressed amplifying stages.
The prior art approach of the fixed-gate-biased transistor (effectively grounded gate for small-signal equivalence) interposed between the grounded-source drain and the output terminal disclosed by Hsu, et al., does reduce the substrate current in the transistor M6 enough to extend the lifetime of the circuit described somewhat. However, transistor M6A itself now may experience a considerable amount of substrate current at peak voltages that eventually may degrade its threshold voltage or shunt conductance sufficiently to unacceptably alter the circuit performance.
Embodiments of the present Cascode circuit bias circuit arrangement invention incorporate a first transistor chain, having at least one additional transistor, connected in series between a Cascode circuit output voltage terminal and the drain of a first transistor in a second cascode transistor series chain where the second cascode transistor chain is connected at its source end to circuit ground). The additional transistor(s) in the first chain is (are) biased by fixed voltages at respective gate terminal(s) to limit respective maximum drain-to-source voltages across two or more individual transistors in the second cascode transistor chain. The maximum drain-to-source voltages are limited to respective maximum values below respective critical voltage levels (Vcrit) at which respective substrate currents in the corresponding two or more individual transistors unacceptably change a circuit performance characteristic, (e.g. gain, output impedance, operational lifetime and the like). Additionally, embodiments of the present invention improve reliability, by postponing the circuit""s end-of-life, i.e., lengthening the time over which selected circuit characteristics meet predetermined levels.